Independent researcher Manjeet Singh and Anthropic’s Claude Opus 4.6 have published a technical reverse-engineering analysis detailing direct API access to Apple’s 16-core M4 Neural Engine. By bypassing the high-overhead CoreML framework, the team enabled direct hardware programming and revealed how the 127-queue-depth chip executes computation graphs. This breakthrough provides developers with a blueprint to unlock raw performance and experiment with model training on hardware previously restricted to inference.
Bypassing CoreML via Private Hardware APIs
Historically, developers running machine learning workloads on Apple Silicon have been forced to go through CoreML, Apple's high-level abstraction framework. CoreML introduces optimization passes and framework overhead that obfuscate hardware mechanics and prevent low-level optimization.
Singh and Claude Opus 4.6 mapped the full software stack down to the IOKit kernel driver using Objective-C class discovery on AppleNeuralEngine.framework. The investigation revealed that by bypassing CoreML using the private _ANEClient API, researchers successfully achieved direct, in-memory program compilation and hardware execution on Apple's M4 Neural Engine.
The direct pipeline bypasses file-system round trips by feeding Machine Learning Intermediate Language (MIL) text directly into _ANEInMemoryModelDescriptor. Workloads are compiled into Apple’s proprietary E5 binary format and evaluated using IOSurface shared memory buffers, enabling zero-copy memory transfers between the ANE and GPU.
The M4 Architecture and Microcode Footprint
The M4 Neural Engine (codenamed H16G) operates not as a general-purpose processor or traditional GPU, but as a dedicated graph execution engine. Rather than executing individual micro-instructions, it processes entire computation graphs atomically.
Analysis of the compiled binaries showed that tensor operations map to fixed compute primitives parameterized at runtime. Key findings from the hardware profiling include:
- Core Topology: 16 dedicated cores featuring hard power gating that reduces idle power draw to 0 milliwatts.
- Queue Capabilities: Hardware support for up to 127 simultaneous in-flight evaluation requests for high-throughput streaming.
- Binary Efficiency: A 1024×1024 matrix multiplication compiles to just 2,688 bytes in E5 binary format, compared to 2,680 bytes for a 128×128 matrix.
- Dynamic Voltage/Frequency: Independent DVFS channels controlled via adaptive clock triggers (ANE_ADCLK_TRIG) and power-performance tuning triggers.
- Primary Compute Primitives: Native hardware support centered around 1×1 convolutions, matrix multiplication, and elementwise functions.